User contributions for Nspiredev500
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27 June 2020
- 17:3917:39, 27 June 2020 diff hist −276 Memory-mapped I/O ports on CX added a link to my new timers page
- 17:3817:38, 27 June 2020 diff hist −279 m Memory-mapped I/O ports on CX added a link to my new timers page
- 17:3817:38, 27 June 2020 diff hist −279 Memory-mapped I/O ports on CX added a link to my new timers page
- 17:3517:35, 27 June 2020 diff hist +737 N Timers Created page with "From my tests it seems all 3 timer modules are equal (the fast timer, the first timer, and the second timer), but the fast timer has a special register set to 0x0.<br> This re..." current
25 June 2020
- 20:4320:43, 25 June 2020 diff hist +349 Memory-mapped I/O ports on CX →900D0000 - Second timer
- 20:4320:43, 25 June 2020 diff hist +349 Memory-mapped I/O ports on CX →900C0000 - First timer
- 20:4220:42, 25 June 2020 diff hist +349 Memory-mapped I/O ports on CX →90010000 - Fast timer
16 April 2020
- 14:0814:08, 16 April 2020 diff hist +68 m Memory-mapped I/O ports on CX At least on HW-AA, the RTC is a standard PL031 with no registers changed.