Virtual Memory: Difference between revisions
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(New page: The ARM926EJ-S MMU is used to map NOR, RAM and peripherals in memory. Virtual memory is split into 1MB sections. The Translation Table Base Register (CP15 register c2) contains the addre...) |
Calc84maniac (talk | contribs) (→0x00000000-0x000FFFFF (1MB) - Internal RAM: whoops, meant 80KB) |
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The ARM926EJ-S MMU is used to map NOR, | The [[Hardware#CPU|ARM926EJ-S]] [[Hardware#MMU|MMU]] is used to map [[Hardware#Boot1 and certificate memory|NOR]], [[Hardware#SDRAM|SDRAM]] and [[Memory-mapped I/O ports|peripherals]] in memory. | ||
Virtual memory is split into 1MB sections. | Virtual memory is split into 1MB sections. | ||
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== 0x00000000-0x000FFFFF (1MB) - | == 0x00000000-0x000FFFFF (1MB) - Internal RAM == | ||
RAM, probably internal to [[Hardware#CPU|ZEVIO ASIC]] | |||
80KB of RAM, the last 16KB of which is repeated 4 times for a total address space of 128KB. | |||
This 128KB is repeated 8 times. | |||
* Physical address : 0xA4000000-0xA40FFFFF | * Physical address : 0xA4000000-0xA40FFFFF | ||
* not cached, not buffered | * not cached, not buffered | ||
== 0x10000000-0x11EFFFFF (31MB) - | == 0x10000000-0x11EFFFFF (31MB) - [[Hardware#SDRAM|SDRAM]] == | ||
First 31MB of RAM | First 31MB of RAM | ||
* Physical address : 0x10000000-0x11EFFFFF | * Physical address : 0x10000000-0x11EFFFFF | ||
* write-back cache | * write-back cache | ||
== 0x11F00000-0x11FFFFFF (1MB) - | == 0x11F00000-0x11FFFFFF (1MB) - [[Hardware#SDRAM|SDRAM]] == | ||
Last 1MB of RAM | Last 1MB of RAM | ||
* Physical address : 0x11F00000-0x11FFFFFF | * Physical address : 0x11F00000-0x11FFFFFF | ||
| Line 28: | Line 32: | ||
* not cached, not buffered | * not cached, not buffered | ||
== 0x18000000-0x180FFFFF (1MB) - alias of | == 0x18000000-0x180FFFFF (1MB) - alias of [[#0x10000000-0x11EFFFFF (31MB) - SDRAM|SDRAM]] == | ||
* Physical address : 0x11E00000-0x11EFFFFF (alias of 0x11E00000-0x11EFFFFF virtual address) | * Physical address : 0x11E00000-0x11EFFFFF (alias of 0x11E00000-0x11EFFFFF virtual address) | ||
* write-back cache | * write-back cache | ||
== 0x8FF00000-0x901FFFFF (3MB) - | == 0x8FF00000-0x901FFFFF (3MB) - [[Memory-mapped I/O ports]] == | ||
[[Memory-mapped I/O ports]] | |||
* Physical address : 0x8FF000000-0x901FFFFF | * Physical address : 0x8FF000000-0x901FFFFF | ||
* not cached, not buffered | * not cached, not buffered | ||
| Line 42: | Line 45: | ||
* not cached, not buffered | * not cached, not buffered | ||
== 0xA4000000-0xA40FFFFF (1MB) - | == 0xA4000000-0xA40FFFFF (1MB) - alias of [[#0x00000000-0x000FFFFF (1MB) - Internal RAM|Internal RAM]] == | ||
[[ | |||
* Physical address : 0xA4000000-0xA40FFFFF (alias of 0x00000000-0x000FFFFF virtual address) | * Physical address : 0xA4000000-0xA40FFFFF (alias of 0x00000000-0x000FFFFF virtual address) | ||
* not cached, not buffered | * not cached, not buffered | ||
| Line 52: | Line 54: | ||
* not cached, not buffered | * not cached, not buffered | ||
== 0xAC000000-0xAC0FFFFF (1MB) - | == 0xAC000000-0xAC0FFFFF (1MB) - [[Memory-mapped I/O ports]] == | ||
[[Memory-mapped I/O ports]] | |||
* Physical address : 0xAC000000-0xAC0FFFFF | * Physical address : 0xAC000000-0xAC0FFFFF | ||
* not cached, not buffered | * not cached, not buffered | ||
== 0xB0000000-0xB00FFFFF (1MB) - | == 0xB0000000-0xB00FFFFF (1MB) - [[Memory-mapped I/O ports]] == | ||
[[Memory-mapped I/O ports]] | |||
* Physical address : 0xB0000000-0xB00FFFFF | * Physical address : 0xB0000000-0xB00FFFFF | ||
* not cached, not buffered | * not cached, not buffered | ||
== 0xB4000000-0xB40FFFFF (1MB) - | == 0xB4000000-0xB40FFFFF (1MB) - [[Memory-mapped I/O ports]] == | ||
[[Memory-mapped I/O ports]] | |||
* Physical address : 0xB4000000-0xB40FFFFF | * Physical address : 0xB4000000-0xB40FFFFF | ||
* not cached, not buffered | * not cached, not buffered | ||
== 0xB8000000-0xB80FFFFF (1MB) - | == 0xB8000000-0xB80FFFFF (1MB) - [[Memory-mapped I/O ports]] == | ||
[[Memory-mapped I/O ports | |||
* Physical address : 0xB8000000-0xB80FFFFF | * Physical address : 0xB8000000-0xB80FFFFF | ||
* not cached, not buffered | * not cached, not buffered | ||
== 0xBC000000-0xBC0FFFFF (1MB) - | == 0xBC000000-0xBC0FFFFF (1MB) - [[Memory-mapped I/O ports]] == | ||
[[Memory-mapped I/O ports | |||
* Physical address : 0xBC000000-0xBC0FFFFF | * Physical address : 0xBC000000-0xBC0FFFFF | ||
* not cached, not buffered | * not cached, not buffered | ||
== 0xC0000000-0xC00FFFFF (1MB) - | == 0xC0000000-0xC00FFFFF (1MB) - [[Memory-mapped I/O ports]] == | ||
[[Memory-mapped I/O ports | |||
* Physical address : 0xC0000000-0xC00FFFFF | * Physical address : 0xC0000000-0xC00FFFFF | ||
* not cached, not buffered | * not cached, not buffered | ||
== 0xC4000000-0xC40FFFFF (1MB) - | == 0xC4000000-0xC40FFFFF (1MB) - [[Memory-mapped I/O ports]] == | ||
[[Memory-mapped I/O ports | |||
* Physical address : 0xC4000000-0xC40FFFFF | * Physical address : 0xC4000000-0xC40FFFFF | ||
* not cached, not buffered | * not cached, not buffered | ||
| Line 92: | Line 87: | ||
* not cached, not buffered | * not cached, not buffered | ||
== 0xCC000000-0xCC0FFFFF (1MB) - | == 0xCC000000-0xCC0FFFFF (1MB) - [[Memory-mapped I/O ports]] == | ||
[[Memory-mapped I/O ports | |||
* Physical address : 0xCC000000-0xCC0FFFFF | * Physical address : 0xCC000000-0xCC0FFFFF | ||
* not cached, not buffered | * not cached, not buffered | ||
== 0xDC000000-0xDC0FFFFF (1MB) - | == 0xDC000000-0xDC0FFFFF (1MB) - [[Memory-mapped I/O ports]] == | ||
[[Memory-mapped I/O ports | |||
* Physical address : 0xDC000000-0xDC0FFFFF | * Physical address : 0xDC000000-0xDC0FFFFF | ||
* not cached, not buffered | * not cached, not buffered | ||
Latest revision as of 18:43, 14 December 2010
The ARM926EJ-S MMU is used to map NOR, SDRAM and peripherals in memory.
Virtual memory is split into 1MB sections.
The Translation Table Base Register (CP15 register c2) contains the address of an array of 4096 words, each one describes a section.
The MMU allows both reads and writes on all mentioned sections, the others will trigger an exception for any access.
0x00000000-0x000FFFFF (1MB) - Internal RAM
RAM, probably internal to ZEVIO ASIC
80KB of RAM, the last 16KB of which is repeated 4 times for a total address space of 128KB. This 128KB is repeated 8 times.
- Physical address : 0xA4000000-0xA40FFFFF
- not cached, not buffered
0x10000000-0x11EFFFFF (31MB) - SDRAM
First 31MB of RAM
- Physical address : 0x10000000-0x11EFFFFF
- write-back cache
0x11F00000-0x11FFFFFF (1MB) - SDRAM
Last 1MB of RAM
- Physical address : 0x11F00000-0x11FFFFFF
- not cached, not buffered
0x12000000-0x17FFFFFF (96MB)
Unknown
- Physical address : 0x12000000-0x17FFFFFF
- not cached, not buffered
0x18000000-0x180FFFFF (1MB) - alias of SDRAM
- Physical address : 0x11E00000-0x11EFFFFF (alias of 0x11E00000-0x11EFFFFF virtual address)
- write-back cache
0x8FF00000-0x901FFFFF (3MB) - Memory-mapped I/O ports
- Physical address : 0x8FF000000-0x901FFFFF
- not cached, not buffered
0xA0000000-0xA00FFFFF (1MB)
I/O ?
- Physical address : 0xA0000000-0xA00FFFFF
- not cached, not buffered
0xA4000000-0xA40FFFFF (1MB) - alias of Internal RAM
- Physical address : 0xA4000000-0xA40FFFFF (alias of 0x00000000-0x000FFFFF virtual address)
- not cached, not buffered
0xA9000000-0xA90FFFFF (1MB)
I/O ?
- Physical address : 0xA9000000-0xA90FFFFF
- not cached, not buffered
0xAC000000-0xAC0FFFFF (1MB) - Memory-mapped I/O ports
- Physical address : 0xAC000000-0xAC0FFFFF
- not cached, not buffered
0xB0000000-0xB00FFFFF (1MB) - Memory-mapped I/O ports
- Physical address : 0xB0000000-0xB00FFFFF
- not cached, not buffered
0xB4000000-0xB40FFFFF (1MB) - Memory-mapped I/O ports
- Physical address : 0xB4000000-0xB40FFFFF
- not cached, not buffered
0xB8000000-0xB80FFFFF (1MB) - Memory-mapped I/O ports
- Physical address : 0xB8000000-0xB80FFFFF
- not cached, not buffered
0xBC000000-0xBC0FFFFF (1MB) - Memory-mapped I/O ports
- Physical address : 0xBC000000-0xBC0FFFFF
- not cached, not buffered
0xC0000000-0xC00FFFFF (1MB) - Memory-mapped I/O ports
- Physical address : 0xC0000000-0xC00FFFFF
- not cached, not buffered
0xC4000000-0xC40FFFFF (1MB) - Memory-mapped I/O ports
- Physical address : 0xC4000000-0xC40FFFFF
- not cached, not buffered
0xC8000000-0xC80FFFFF (1MB)
I/O ?
- Physical address : 0xC8000000-0xC80FFFFF
- not cached, not buffered
0xCC000000-0xCC0FFFFF (1MB) - Memory-mapped I/O ports
- Physical address : 0xCC000000-0xCC0FFFFF
- not cached, not buffered
0xDC000000-0xDC0FFFFF (1MB) - Memory-mapped I/O ports
- Physical address : 0xDC000000-0xDC0FFFFF
- not cached, not buffered