Clock speed: Difference between revisions

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This document describes the format for clock speed load values. The clock speed can be set by writing to the first two registers at [[Memory-mapped_I/O_ports#900B0000_-_Power_management]]. Clock speeds are in units of MHz. Most of this information is derived from Nover source code.
This document describes the format for clock speed load values. The clock speed can be set by writing to the first two registers at [[Memory-mapped_I/O_ports#900B0000_-_Power_management]]. Clock speeds are in units of MHz. Most of this information is derived from Nover and nspire_emu source code.


==CX model==
==CX model==
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{|class="wikitable"
{|class="wikitable"
|-
|-
! Bit || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || 10 || 11 || 12 || 13 || 14 || 15 || 16 || 17 || 18 || 19 || 20 || 21 || 22
! Bit || 0 || 1 || 2 || 3 || 4 || 5 || 6 || 7 || 8 || 9 || 10 || 11 || 12 || 13 || 14 || 15 || 16 || 17 || 18 || 19 || 20 || .. || 30 || 31
|-
|-
| ||  || colspan="7"| Base/CPU value || 48MHz base || colspan="3"| || colspan="3"| CPU/AHB value || colspan="6"| Base value || colspan="2"|Unknown
| ||  || colspan="7"| Base/CPU value || 48MHz base || colspan="3"| || colspan="3"| CPU/AHB value || colspan="6"| Base value || || colspan="2"|Unknown
|}
|}


{|class="wikitable"
{|class="wikitable"
|-
|-
| Base to CPU ratio || (Base/CPU value) * (Unknown)
| Base to CPU ratio (if 48MHz base) || 1 << (Unknown)
|-
|-
| CPU to AHB ratio (if 48MHz base) || 2
|-
| Base clock speed (if 48MHz base) || 48
|-
| Base to CPU ratio || (Base/CPU value)*2 or 2 if 0
|-
| CPU to AHB ratio || (CPU/AHB value) + 1
| CPU to AHB ratio || (CPU/AHB value) + 1
|-
| Base clock speed (if 48MHz base) || 48
|-
|-
| Base clock speed || 6 * (Base value)
| Base clock speed || 6 * (Base value)

Latest revision as of 13:33, 20 July 2015

This document describes the format for clock speed load values. The clock speed can be set by writing to the first two registers at Memory-mapped_I/O_ports#900B0000_-_Power_management. Clock speeds are in units of MHz. Most of this information is derived from Nover and nspire_emu source code.

CX model

Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 .. 30 31
Base/CPU value 48MHz base CPU/AHB value Base value Unknown
Base to CPU ratio (if 48MHz base) 1 << (Unknown)
CPU to AHB ratio (if 48MHz base) 2
Base clock speed (if 48MHz base) 48
Base to CPU ratio (Base/CPU value)*2 or 2 if 0
CPU to AHB ratio (CPU/AHB value) + 1
Base clock speed 6 * (Base value)
CPU clock speed (Base clock speed) / (Base to CPU ratio)
AHB clock speed (CPU clock speed) / (CPU to AHB ratio)
APB clock speed (AHB clock speed) / 2

The unknown quantity only ever seems to be either 1 or 2. It's probably a multiplier.

Classic model

Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Base/CPU value 27MHz base CPU/AHB value Base value
Base to CPU ratio (Base/CPU value) * 2
CPU to AHB ratio (CPU/AHB value) + 1
Base clock speed (if 27MHz base) 27
Base clock speed 300 - 6 * (Base value)
CPU clock speed (Base clock speed) / (Base to CPU ratio)
AHB clock speed (CPU clock speed) / (CPU to AHB ratio)
APB clock speed (AHB clock speed) / 2