Memory-mapped I/O ports: Difference between revisions

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(add all known address areas containing I/O ports, plus documentation for some of the better understood areas)
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== 8FFF0000 - Unknown ==
This page was split:


== 90000000 - General Purpose I/O (GPIO) ==
[[Memory-mapped I/O ports on Classic]]


== 90020000 - Serial UART ==
[[Memory-mapped I/O ports on CX]]
Used to communicate with the [[Hardware#RS232|RS232 serial port]]. The register interface is like that of 16550 UART used in PCs:
* 90020000 (R): Receiver Buffer Register
* 90020000 (W): Transmitter Holding Register
* 90020004 (R/W): Interrupt Enable Register
* 90020008 (R): Interrupt Identification Register
* 90020008 (W): FIFO Control Register
* 9002000C (R/W): Line Control Register
* 90020010 (R/W): Modem Control Register
* 90020014 (R): Line Status Register
* 90020018 (R): Modem Status Register
* 9002001C (R/W): Scratch Register


== 90080000 - Unknown ==
[[Memory-mapped I/O ports on CX II]]
 
== 90090000 - Real-Time Clock (RTC) ==
* 90090000 (R): Current time in seconds
* 90090004 (W): ?
* 90090008 (W): ?
* 9009000C (W): ?
* 90090010 (W): ?
* 90090014 (R): ?
 
== 900A0000 - Miscellaneous ==
* 900A0000 (R): ?
* 900A0004 (R/W): ?
* 900A0008 (W): Write a 2 to reset the CPU
* 900A0018 (W): Reset first timer interrupt?
* 900A001C (W): ?
* 900A0020 (W): Reset second timer interrupt?
* 900A0024 (W): ?
* 900A0028-900A002C (R):
** These registers together give a 64-bit number which comprises 56 data bits and 8 parity checking bits:
*** Bit 0 is a parity check of all data bits
*** Bits 1, 2, 4, 8, 16, and 32 are parity checks of the data bits whose positions, expressed in binary, have that respective bit set.
*** Bit 63 is a parity check of bits 1, 2, 4, 8, 16, and 32.
** With this system, any single-bit error can be detected and corrected.
** Data bits 58-62 are the "ASIC user flags", a byte which must match the 80E0 field in an OS image. 01 = CAS, 00 = non-CAS.
 
== 900B0000 - Power management ==
* 900B0000 (R/W): Clock speeds
** Bits 1-7:  Multiply by 2 to get base/CPU ratio
** Bit 8:      If set, base clock is 27 MHz, else see bits 16-20
** Bits 12-14: Add 1 to get CPU/AHB ratio
** Bits 16-20: If bit 8 is clear, base clock is (300 - 6*this) MHz
* 900B0004 (W): ?
* 900B0008 (R/W): ?
* 900B000C (R/W): ?
* 900B0014 (W): ?
* 900B0018 (R/W): ?
* 900B0020 (R/W): ?
* 900B0028 (R): ?
 
== 900C0000 - First timer ==
 
== 900D0000 - Second timer ==
 
==0x900E0010-0x900E001F - Keypad==
(Read?)-Write, half-word (only?)
 
Keypad map. Each bit represents a key. If bit is cleared, the key is being pressed. Only bit 0 to 11 are used. The mapping depends on the currently used keypad (TI-Nspire or TI-84+).
 
'''TI-Nspire keypad map:'''
{|border="1" cellspacing="0" cellpadding="5"
|-
! offset
! bit 0
! bit 1
! bit 2
! bit 3
! bit 4
! bit 5
! bit 6
! bit 7
! bit 8
! bit 9
! bit 10
! bit 11
|-
| 0010
| ret
| enter
| space
| (-)
| Z
| .
| Y
| 0
| X
| ---
| theta
| on
|-
| 0012
| ,
| +
| W
| 3
| V
| 2
| U
| 1
| T
| e^x
| pi
| click
|-
| 0014
| ?
| -
| S
| 6
| R
| 5
| Q
| 4
| P
| 10^x
| EE
| ---
|-
| 0016
| :
| *
| O
| 9
| N
| 8
| M
| 7
| L
| x^2
| i
| ---
|-
| 0018
| "
| /
| K
| tan
| J
| cos
| I
| sin
| H
| ^
| >
| ---
|-
| 001A
| '
| cat
| G
| )
| F
| (
| E
| var
| D
| caps
| <
| ---
|-
| 001C
| flag
| ---
| C
| home
| B
| menu
| A
| esc
| &#124;
| tab
| =
| ---
|-
| 001E
| up
| ---
| right
| ---
| down
| ---
| left
| ---
| clear
| ctrl
| =
| ---
|}
 
 
'''TI-84+ keypad map:'''
{|border="1" cellspacing="0" cellpadding="5"
|-
! offset
! bit 0
! bit 1
! bit 2
! bit 3
! bit 4
! bit 5
! bit 6
! bit 7
! bit 8
! bit 9
! bit 10
! bit 11
|-
| 0010
| down
| left
| right
| up
| ---
| ---
| ---
| ---
| ---
| ---
| ---
| on
|-
| 0012
| enter
| +
| -
| *
| /
| ^
| clear
| ---
| ---
| ---
| ---
| ---
|-
| 0014
| (-)
| 3
| 6
| 9
| )
| tan
| vars
| ---
| ---
| ---
| ---
| ---
|-
| 0016
| .
| 2
| 5
| 8
| (
| cos
| prgm
| stat
| ---
| ---
| ---
| ---
|-
| 0018
| 0
| 1
| 4
| 7
| ,
| sin
| apps
| X
| ---
| ---
| ---
| ---
|-
| 001A
| ---
| sto
| ln
| log
| x^2
| x^-1
| math
| alpha
| ---
| ---
| ---
| ---
|-
| 001C
| graph
| trace
| zoom
| wind
| y=
| 2nd
| mode
| del
| ---
| ---
| ---
| ---
|-
| 001F
| ---
| ---
| ---
| ---
| ---
| ---
| ---
| ---
| ---
| ---
| ---
| ---
|}
 
== 900F0000 - Unknown ==
 
== 90100000 - TI-84 Plus link port ==
 
== A4000100-A40096FF - Screen ==
Read-write, byte, half-word, word
 
Screen buffer. The upper left corner is the first byte. Each grayscaled pixel is 4-bit long. 1111 is white, 0000 is black.
 
== AC000000 - Unknown ==
 
== B0000000 - First USB ==
 
== B4000000 - Second USB ==
 
== B8000000 - NAND Flash ==
 
== BC000000 - Unknown ==
 
== C0000000 - LCD controller ==
Probably an [http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0161e/index.html ARM PrimeCell PL110] or something compatible.
 
== C4000000 - Analog-to-Digital Converter (ADC) ==
 
== CC000000 - SHA-256 hash generator ==
Implements the [http://en.wikipedia.org/wiki/SHA_hash_functions SHA-256 hash algorithm], which is used in cryptographic signatures.
 
* CC000000 (R): Busy if bit 0 set
* CC000000 (W): Write 0x10 and then 0x0 to initialize. Write 0xE to process first block, 0xA to process subsequent blocks
* CC000008 (R/W): ?
* CC000010-CC00004F (W): 512-bit block
* CC000060-CC00007F (R): 256-bit state
 
== DC000000 - Interrupt controller ==
Registers that operate on sets of IRQs are bitmaps, with bit 0 corresponding to IRQ 0, and so on.
 
* DC000004 (W): Acknowledge a set of IRQs
* DC000008 (R): Current set of enabled IRQs
* DC000008 (W): Enable a set of IRQs
* DC00000C (W): Disable a set of IRQs
* DC000020 (R): ?
* DC000024 (R): Current IRQ number
* DC000028 (R): ?
* DC00002C (W): ?
* DC000200 (R/W): ?
* DC000204 (R/W): ?
* DC000208 (R/W): ?
* DC000300-DC0003FF (W): ? (one register per IRQ)
 
Here is a list of known IRQ numbers:
 
* IRQ 1 = [[#90020000 - Serial UART|Serial UART]]
* IRQ 7 = [[#90000000 - General Purpose I/O (GPIO)|GPIO]]
* IRQ 8 = [[#B0000000 - First USB|First USB]]
* IRQ 9 = [[#B4000000 - Second USB|Second USB]]
* IRQ 11 = [[#C4000000 - Analog to Digital Converter (ADC)|ADC]]
* IRQ 18 = [[#900C0000 - First timer|First timer]]
* IRQ 19 = [[#900D0000 - Second timer|Second timer]]

Latest revision as of 17:05, 3 July 2019

This page was split:

Memory-mapped I/O ports on Classic

Memory-mapped I/O ports on CX

Memory-mapped I/O ports on CX II

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